SystemVerilog - CaLiGraph

CaLiGraph

Property	Value
rdf:type	owl:NamedIndividual Concurrent and parallel programming language Hardware verification language System description language Programming language created in 2002
rdfs:label	SystemVerilog
owl:sameAs	dbr:SystemVerilog
prov:wasDerivedFrom	http://en.wikipedia.org/wiki/Mixin http://en.wikipedia.org/wiki/Category:Programming_languages_created_in_2002 http://en.wikipedia.org/wiki/List_of_programming_languages_by_type http://en.wikipedia.org/wiki/Augmented_assignment http://en.wikipedia.org/wiki/Dataflow_programming http://en.wikipedia.org/wiki/List_of_concurrent_and_parallel_programming_languages http://en.wikipedia.org/wiki/Hardware_description_language http://en.wikipedia.org/wiki/ModelSim http://en.wikipedia.org/wiki/Open_Verification_Library http://en.wikipedia.org/wiki/Property_Specification_Language http://en.wikipedia.org/wiki/Accellera http://en.wikipedia.org/wiki/Category:Hardware_verification_languages http://en.wikipedia.org/wiki/Category:System_description_languages
skos:prefLabel	SystemVerilog
skos:altLabel	Constrained random generation in SystemVerilog
clgo:designer	Synopsys Institute of Electrical and Electronics Engineers
clgo:influencedBy	Verilog VHDL OpenVera Java (programming language) C++
clgo:latestReleaseDate	2018-02-22
clgo:latestReleaseVersion	IEEE 1800-2017
is clgo:influenced of	Verilog

About: clgr:SystemVerilog